Search Results
5 recordsMedian $169,834Avg $169,834Min $162,086Max $175,000
Showing 1–5 of 5 results
| Employer | Job Title | Base Salary ↓ | City / State | Year | Submitted | Start Date |
|---|---|---|---|---|---|---|
| Palo Alto Networks, Inc | Senior ASIC Design Verification Engineer | $175,000 | Santa Clara, CA | 2020 | 2020-10-27 | 2020-11-03 |
| Palo Alto Networks, Inc | Senior ASIC Design Verification Engineer | $175,000 | Santa Clara, CA | 2020 | 2020-10-27 | 2020-11-03 |
| Palo Alto Networks, Inc | Senior ASIC Design Verification Engineer | $175,000 | Santa Clara, CA | 2020 | 2020-10-27 | 2020-11-03 |
| Palo Alto Networks, Inc | Senior ASIC Design Verification Engineer | $162,086 | Santa Clara, CA | 2024 | 2024-06-04 | 2024-06-12 |
| Palo Alto Networks, Inc | Senior ASIC Design Verification Engineer | $162,086 | Santa Clara, CA | 2024 | 2024-06-04 | 2024-06-12 |